1. Field of the Invention
This invention relates to a phase locked loop (hereinafter referred to as PLL) circuit and an optical communications receiving apparatus, and more particularly, to a PLL circuit having a phase detection circuit and a frequency detection circuit, and an optical communications receiving apparatus employing such PLL circuit as a generation circuit of a clock signal required for a re-timing processing upon receiving data.
2. Description of the Related Art
FIG. 14 shows a configuration of a conventional PLL circuit generally available at the present. The PLL circuit shown in FIG. 14 has a phase detection (PD) circuit 101 and a frequency detection (FD) circuit 102, and is operated as follows.
First, a frequency comparison of an input signal DATA with each clock signal (ICLK, QCLK) is executed in the frequency detection circuit 102. Then, based on a result of the above mentioned frequency comparison, a frequency of an oscillation frequency clock VCOCLK of a voltage-controlled oscillator (hereinafter referred to as VCO) 106 is pulled into an objective oscillation frequency by controlling the frequency of the oscillation frequency clock VCOCLK through a charge pump (CP) circuit 104 and a loop filter 105. In addition, the clock signals (ICLK, QCLK) are generated in a clock generator 107 on the basis of the oscillation frequency clock VCOCLK of the VCO 106.
Subsequently, a phase comparison of the input signal DATA with the oscillation frequency clock VCOCLK of the VCO 106 is executed in the phase detection circuit 101. Then, based on a result of the above mentioned phase comparison, the phase of the oscillation frequency clock VCOCLK of the VCO 106 is coincided with the phase of the input signal DATA by controlling the phase of the oscillation frequency clock VCOCLK of the VCO 106 through a charge pump circuit 103 and the loop filter 105.
In the PLL circuit of this kind, a circuit having a configuration as shown in FIG. 15 has been conventionally used as the frequency detection circuit 102. A specific circuit configuration of the frequency detection circuit 102 shown in FIG. 15 and the operation thereof will be now described.
In the PLL circuit shown in FIG. 15, assume that a digital signal DATA having non-return-to-zero (hereinafter referred to as NRZ) waveform is to be supplied to the frequency detection circuit 102. It is also assumed that the clock generator 107 provides the clock signal ICLK obtained by dividing the oscillation frequency clock VCOCLK of the VCO 106 at a predetermined dividing ratio 1/n (n=1 in this case), and also provides the clock signal QCLK obtained by shifting a phase of the clock signal ICLK by 90 degrees, and these clock signals ICLK and QCLK are to be supplied to the frequency detection circuit 102.
A data input terminal 111 to which the input signal DATA of the NRZ waveform is supplied is connected to a data input terminal (hereinafter referred to as D input terminal) of a D type flip-flop (hereinafter referred to as D-FF) 112, and also connected to one input terminal A of an exclusive-OR (hereinafter referred to as EX-OR) gate 113. On the one hand, an ICLK input terminal 114 to which the clock signal ICLK is supplied is connected to one input terminal A of each AND gate 116 and 117, and a QCLK input terminal 115 to which the clock signal QCLK is supplied is connected to the other input terminal B of each AND gate 116 and 117. In this case, the one input terminal A of the AND gate 117 is an inverting input terminal to which the clock signal ICLK with an inverted polarity thereof is supplied.
Respective output terminals of the AND gates 116 and 117 are connected to respective D input terminals of D-FFs 118 and 119. An output terminal of the EX-OR gate 113 is connected to a clock input terminal (hereinafter referred to as CLK input terminal) of each of the D-FFs 118 and 119. Respective Q output terminals of the D-FFs 118 and 119 are connected to respective D input terminals of D-FFs 120 and 121, and respective Q output terminals of the D-FF 120 and D-FF 121 are connected to respective D input terminals of D-FF 122 and D-FF 123. In addition, respective CLK terminals of the D-FFs 112 and 120 to 123 are connected to the ICLK input terminal 114.
A Q output terminal of the D-FF 122 is connected to one input terminal A of an AND gate 124. A Q output terminal of the D-FF 123 is connected to the other input terminal B of an AND gate 125. The Q output terminal of the D-FF 120 is further connected to one input terminal A of the AND gate 125, and the Q output terminal of the D-FF 121 is further connected to the other input terminal B of the AND gate 124. In addition, output terminals of each of the AND gates 124 and 125 are connected to circuit output terminals 126 and 127.
Further, a DOWN pulse signal that controls the oscillation frequency of the VCO 106 in FIG. 14 so as to set the oscillation frequency thereof lower is derived from the AND gate 124 as an output signal thereof. In addition, an UP pulse signal that controls the oscillation frequency of the VCO 106 so as to set the oscillation frequency thereof higher is derived from the AND gate 125 as an output signal thereof. Then, the DOWN pulse signal and the UP pulse signal are supplied to the charge pump circuit 104 in FIG. 14 through the circuit output terminals 126 and 127.
A circuit operation of the frequency detection circuit 102 having the above configuration will be now described with reference to a timing chart depicted in FIG. 16. Incidentally, reference codes (a) to (o) in the timing chart of FIG. 16 respectively represent waveforms as those of nodes shown by reference codes (a) to (o) in FIG. 15.
A clock signal ICLK (a) is a signal of a pulse waveform, which rises to a high level (hereinafter referred to as “H” level) at a point of a time t0, and falls to a low level (hereinafter referred to as “L” level) at a point of a time t2. In the following, the clock signal ICLK (a) also rises to the “H” level at points of time t4, t8, t12, . . . and falls to the “L” level at points of time t6, t10, . . . likewise. The clock signal ICLK (a) is supplied to the one input terminal A of each of the AND gates 116 and 117 through the ICLK input terminal 114 and also to the CLK terminal of each of the D-FFs 112 and 120 to 123.
A clock signal QCLK (b) is a signal of a pulse waveform whose phase is shifted, specifically, delayed by 90 degrees to the clock signal ICLK (a). In other words, the clock signal QCLK (b) rises to the “H” level at the points of time t1, t5, t9, . . . and falls to the “L” level at the points of time t3, t7, t11, . . . . The clock signal QCLK (b) is supplied to the other input terminal B of each of the AND gates 116 and 117 through the QCLK input terminal 115.
The AND gate 116 is supposed to generate a logical product of the clock signals ICLK (a) and QCLK (b), so that an output signal (c) of the AND gate 116 becomes “H” as long as both the clock signals ICLK (a) and QCLK (b) are of the “H” level, in other words, in a period between the points of time t1 and t2, a period between the points of time t5 and t6, and a period between the points of time t9 and t10. On the contrary, the output signal (c) thereof is supposed to become “L” in the other periods such as a period between the points of time t0 and t1, a period between the points of time t2 and t5, a period between the points of time t6 and t9, and a period between the points of time t10 and t12.
On the other hand, the AND gate 117 is supposed to generate a logical product of an inverted clock signal ICLKX of the clock signal ICLK (a) and the clock signal QCLK (b), so that an output signal (d) of the AND gate 117 becomes “H” as long as both the clock signals ICLKX and QCLK (b) are at the “H” level, in other words, in the period between the points of time t2 and t3, the period between the points of time t6 and t7 and the period between the points of time t10 and t11. On the contrary, the output signal (d) thereof is supposed to become “L” in the other periods such as a period between the points of time t0 and t2, a period between the points of time t3 and t6, a period between the points of time t7 and t10, and a period on and after the point of time t11.
In the timing chart of FIG. 16, a “H” level period of the output signal (c) is represented as a period A, and a “H” level period of the output signal (d) is represented as a period B.
On the one hand, an input signal DATA (f) of an NRZ waveform provided to the data input terminal 111 is directly supplied to one input terminal A of the EX-OR gate 113 and also to the D input terminal of the D-FF 112. The D-FF 112 samples, at the point of time on the leading edge of the clock signal ICLK, a “H” level or a “L” level value of the input waveform supplied to the D input terminal thereof. In this case, if the input signal DATA (f) is supposed to be at the “H” level at the point of time t0, by sampling a “H” level value of the input signal DATA (f), a Q output signal (e) of the D-FF 112 becomes “H”.
In addition, the input signal DATA (f) is varied between the points of time t1 and t2 to invert the polarity, so that a “L” level value of the “L” level input signal DATA (f) is sampled at the point of time t4 on the next leading edge of the clock signal ICLK (a), thereby the Q output signal (e) of the D-FF 112 makes the transition from the “H” level to the “L”°level. Furthermore, an inverting of the polarity of the input signal DATA (f) occurs again between the points of time t6 and t7, so that the “H” level value of the “H” level input signal DATA (f) is sampled at the point of time t8 on the next leading edge of the clock signal ICLK (a), thereby the Q output signal (e) of the D-FF 112 makes the transition from the “L” level to the “H” level. Thereafter, the Q output signal (e) maintains the “H” level up to the point of time t12.
The Q output signal (e) of the D-FF 112 is supplied to the other input terminal B of the EX-OR gate 113, and an exclusive logical sum operation of the Q output signal (e) with the input signal DATA (f) supplied to one input terminal A of the EX-OR gate 113 is executed in the EX-OR gate 113. As a result, an output signal (g) of the EX-OR gate 113 makes the transition from the “L” level to the “H” level at the point of time when the inverting of the input signal DATA (f) is supposed to occur between the points of time t1 and t2 and, on the contrary, from the “H” level to the “L” level at the point of time t4 when the Q output signal (e) of the D-FF 112 is supposed to make the transition from the “H” level to the “L” level, as clearly shown in the timing chart of FIG. 16.
The output signal (g) of the EX-OR gate 113 maintains the “L” level in the period between the point of time t4 and the point of time at which the inverting of the input signal DATA (f) is supposed to occur again. When the inverting of the input signal DATA (f) occurs again between the points of time t6 and t7, the output signal (g) of the EX-OR gate 113 makes the transition from the “L” level to the “H” level at the point of time of the inverting thereof.
Subsequently, when the point of time t8 comes, the Q output signal (e) of the D-FF 112 is supposed to make the transition from the “L” level to the “H” level, so that the exclusive logical sum operation of the “H” level value of the input signal DATA (f) with the “H” level value of the Q output signal (e) is executed, thereby the output signal (g) of the EX-OR gate 113 makes the transition from the “H” level to the “L” level. Then, the level of the output signal (g) of the EX-OR gate 113 remains unchanged in the subsequent period between the points of time t8 and t12.
The output signals (c) and (d) of the AND gates 116 and 117 are respectively supplied to the D input terminals of the next-stage D-FFs 118 and 119. The D-FFs 118 and 119 are configured to allow the output signal (g) of the EX-OR gate 113 to enter as CLK inputs and thus sample, at the point of the leading edge of the clock waveform of the output signal (g), the waveforms supplied to the D input terminal thereof, thereby deriving the levels thereof as Q output signals (h) and (k).
In this case, the output signal (g) of the EX-OR gate 113 is raised in the period between the points of time t1 and t2, and the output signal (c) of the AND gate 116 and the output signal (d) of the AND gate 117 are respectively at the “H” level and the “L” level in this period, so that the output signal (h) of the D-FF 118 and the Q output signal (k) of the D-FF 119 respectively become “H” and “L”.
A change point of the input signal DATA (f) in the period between the points of time t6 and t7 is the point of time at which the output signal (g) of the EX-OR 113 is supposed to make the next transition from the “L” level to the “H” level. The output signal (c) of the AND gate 116 and the output signal (d) of the AND gate 117 at this point of time are respectively at the “L” level and the “H” level, so that the Q output signal (h) of the D-FF 118 and the output signal (k) of the D-FF 119 respectively make the transition from the “H” level to the “L” level and from the “L” level to the “H” level, and thereafter, maintain the “L” level and the “H” level up to the point of time t12.
The Q output signals (h) and (k) of the D-FFs 118 and 119 are respectively supplied to the D input terminals of the D-FFs 120 and 121. The D-FFs 120 and 121 are configured to allow the clock signal ICLK (a) to enter as CLK input and thus sample, at the point of time on the leading edge of the waveform of the clock signal ICLK (a), the waveforms supplied to the D input terminals thereof. In this case, the time t4 is the point of time on the next leading edge of the clock signal ICLK (a), and the Q output signal (h) of the D-FF 118 and the Q output signal (k) of the D-FF 119 at this point of time are respectively at the “H” level and the “L” level, so that a Q output signal (i) of the D-FF 120 and a Q output signal (l) of the D-FF 121 respectively become “H” and “L”.
The time t8 is the point of time on the next leading edge of the clock signal ICLK (a), and the Q output signal (h) of the D-FF 118 and the Q output signal (k) of the D-FF 119 at this point of time are respectively at the “L” level and the “H” level, so that the Q output signal (i) of the D-FF 120 and the Q output signal (l) of the D-FF 121 respectively make the transition from the “H” level to the “L” level and from the “L” level to the “H” level and thereafter, maintain the “L” level and the “H” level up to the point of time t12.
The Q output signals (i) and (l) of the D-FFs 120 and 121 are respectively supplied to the D input terminals of the next-stage D-FFs 122 and 123. The D-FFs 122 and 123 are also configured to allow the clock signal ICLK (a) to enter as CLK input and thus sample, at the point of time on the leading edge of the waveform of the clock signal LCLK (a), the waveforms supplied to the D input terminals thereof. In this case, the time t8 is the point of time on the leading edge of the clock signal ICLK (a), so that the level values of the Q output signals (i) and (l) of the D-FFs 120 and 121 at this point of time are supposed to be sampled. As a result, a Q output signal (j) of the D-FF 122 and a Q output signal (m) of the D-FF 123 respectively become “H” and “L”.
The time t12 is the point of time on the next leading edge of the clock signal ICLK (a), and the Q output signal (i) of the D-FF 120 and the Q output signal (l) of the D-FF 121 at this point of time are respectively at the “L” level and the “H” level, so that the Q output signal (j) of the D-FF 122 and the Q output signal (m) of the D-FF 123 respectively make the transition from the “H” level to the “L” level and from the “L” level to the “H” level.
The Q output signal (j) of the D-FF 122 is supplied to the input terminal A of the AND gate 124. The Q output signal (l) of the D-FF 121 is supplied to the input terminal B of the AND gate 124. This allows the Q output signal (l) of the D-FF 121 to make the transition to the “L” level at the point of time t4, so that an output signal (n) of the AND gate 124, that is, the DOWN pulse signal becomes “L”. When the point of time t8 comes, the Q output signals (l) and (j) of the D-FFs 121 and 122 are supposed to make the transition to the “H” level, so that the output signal (n) of the AND gate 124 also makes the transition from the “L” level to the “H” level.
When the point of t12 comes, the Q output signal (j) of the D-FF 122 is supposed to make the transition from the “H” level to the “L” level, whereas the Q output signal (l) of the D-FF 121 is still at the “H” level. Thus, the output signal (n) of the AND gate 124, that is, the DOWN pulse signal makes the transition from the “H” level to the “L” level.
On the one hand, the Q output signal (m) of the D-FF 123 is supplied to the input terminal B of the AND gate 125. The Q output signal (i) of the D-FF 120 is supplied to the input terminal A of the AND gate 125. This allows the Q output signals (i) and (m) of the D-FFs 120 and 123 to make the transition from the “H” level to the “L” level at the point of time t8, so that an output signal (o) of the AND gate 125, that is, the UP pulse signal becomes “L”. Then, when the point of time t12 comes, the Q output signal (m) of the D-FF 123 is supposed to make the transition from the “L” level to the “H” level, whereas the Q output signal (i) of the D-FF 120 is still at the “L” level, so that the output signal (o) of the AND gate 125 also maintains the “L” level.
In view of the above, an operation of the frequency detection circuit shown in FIG. 15 will be summarized as follows. Sampling (ICLK, QCLK)=(1,1) at a DATA change point followed by a certain DATA change point at which (ICLK, QCLK)=(0,1) is supposed to be sampled provides output of the UP pulse signal whose length is equivalent to a period of the clock signal ICLK. In other words, in the presence of m (m being an optional integer)-bit data between the two DATA change points, the clock signal ICLK in the period between the two DATA change points is supposed to be present in not more than m cycles, so that the pulse of the UP pulse signal is generated to set the frequency of the clock signal ICLK higher.
Alternatively, sampling (ICLK, QCLK)=(0,0) at the DATA change point followed by the certain DATA change point at which (ICLK, QCLK)=(0,1) is supposed to be sampled provides output of the DOWN pulse signal whose length is equivalent to a period of the clock signal ICLK. In other words, in the presence of m′ (m′ being an optional integer)-bit data between the two DATA change points, the clock signal ICLK in the period between the two DATA change points is supposed to be present in not less than m′ cycles, so that the pulse of the DOWN pulse signal is generated to set the frequency of the clock signal ICLK lower.
When a complete coincidence of frequency between the clock signal ICLK and the input signal DATA is provided, the frequency detection circuit 102 keeps sampling any of (0,0), (0,1), (1,0) and (1,1) at the DATA change point, thereby eliminating the generation of the pulse of the UP pulse signal or the DOWN pulse signal.
As described above, the output signal (n) of the AND gate 124 and the output signal (o) of the AND gate 125 are respectively supplied as the DOWN pulse signal and the UP pulse signal to the charge pump circuit 104 in FIG. 14. Then, these DOWN/UP pulse signals are used to control the charge pump circuit 104 for smoothening (rectifying) an output current thereof, so that a control voltage of the VCO 106 is generated through the loop filter 105.
The above description has been given of the operation of the frequency detection circuit 102 in a case where duty ratios of the input signal DATA and each clock signal (ICLK, QCLK) are respectively assumed to be 100% and 50%. However, in optical communications or the like in particular, a duty distortion occurs in the transmitting signal DATA as shown in (b) and (c) in FIG. 17, so that the possibility exists that the PLL circuit may malfunction. FIG. 18 shows waveforms of the clock signals ICLK and QCLK and the transmitting signal DATA in the presence of the duty distortion.
As described above, the values of the clock signals ICLK and QCLK are sampled in the frequency detection circuit 102 of the related art at the change point of the input signal DATA. Thus, when the complete coincidence of frequency is provided, the sampled values of the clock signals ICLK and QCLK are respectively “0” and “1” at the change point between the corresponding points of time t2 and t3 to those in FIG. 16. In addition, the sampled values of the clock signals ICLK and QCLK are respectively “0” and “1” at the next change point between the points of time t6 and t7. Further, if the DATA change point is also present between the points of time t10 and t11, the sampled values of the clock signals ICLK and QCLK at this change point are also respectively “0” and “1”. Accordingly, it may be proved that the sampled values at the above three change points are all the same.
However, as clearly shown by a timing chart of FIG. 18 showing a timing relation when the distortion occurs in each of the input signals DATA whose duty ratios are different, the clock signal QCLK is supposed to be a signal of a waveform whose phase is delayed by 90 degrees to the clock signal ICLK, and the duty ratio of the input signal DATA becomes greater as against clock signal QCLK so as to provide the input signal DATA whose width of “H” level equivalent to one bit is greater than the period of the clock signal ICLK. In this case, if the leading edge of the input signal DATA is provided between the points of time t1 and t2, the level values of the clock signals ICLK and QCLK at the point of time on the leading edge thereof are respectively “1” and “1”.
Subsequently, both the level values of the clock signals ICLK and QCLK are respectively changed to “0” at the point of time on the trailing edge of the input signal DATA in the period between the points of time t7 and t8. Thus, the sampled values of the clock signals ICLK and QCLK at the points of time on the leading and trailing edges of the input signal DATA are subject to variations from (1, 1) to (0, 0), and as a result, it is proved that the frequency detection circuit may malfunction.
On the other hand, when the duty ratio of the input signal DATA becomes smaller so as to provide the input signal DATA whose width of “H” level equivalent to one bit is smaller than the period of the clock signal ICLK, both the level values of the clock signals ICLK and QCLK are respectively “0” at the point of time on the leading edge of the input signal DATA in the period between the points of time t3 and t4, as shown in FIG. 18. However, both the level values of the clock signals ICLK and QCLK are respectively changed to “0” at the point of time on the trailing edge of the input signal DATA in the period between the points of time t5 and t6. Thus, the sampled values of the clock signals ICLK and QCLK are subject to variations from (0,0) to (1,1), and as a result, the frequency detection circuit may malfunction.
A general configuration of the phase detection circuit 101 will be now described. FIG. 19 is a block diagram showing a circuit configuration of the phase detection circuit 101. The circuit configuration of the phase detection circuit 101 will be described at first.
In FIG. 19, a data input terminal 131 to which the input signal DATA is supplied is connected to a D input terminal of a D-FF 133 and also to one input terminal A of a dual-input exclusive OR (hereinafter referred to as EX-OR) gate 135. On the one hand, a CLK input terminal 132 to which the oscillation frequency clock VCOCLK of the VCO 106 is supplied is connected to a CLK terminal of the D-FF 133 and also to an inverting CLK terminal of a D-FF 134.
A Q output terminal of the D-FF 133 is connected to the other input terminal B of the EX-OR gate 135, one input terminal A of a dual-input EX-OR gate 136 and a D input terminal of the D-FF 134. A Q output terminal of the D-FF 134 is connected to the other input terminal B of the EX-OR gate 136. An output terminal of the EX-OR gate 135 is connected to an UP output terminal 137, and an output terminal of the EX-OR gate 136 is connected to a DOWN-output terminal 138.
Subsequently, a circuit operation of the phase detection circuit 101 having the above configuration will be described with reference to a timing chart of FIG. 20. Incidentally, reference codes (a) to (f) in the timing chart of FIG. 20 respectively represent waveforms as those of nodes shown by reference codes (a) to (f) in FIG. 19.
Now assume that the times t0, t2, t4, t6, t8, t10, t12 and t14 are the points of time on the leading edge of an oscillation frequency clock VCOCLK (a) supplied from the VCO 106 (See FIG. 14) through the CLK input terminal 132, and the times t1, t3, t5, t7, t9, t11, t13 and t15 are the points of time on the trailing edge thereof.
An input signal DATA (b) is a signal of a waveform, which is supposed to be on the “L” level in the period between the trailing edge between the points of time t1 and t2 and the leading edge between the points of time t5 and t6, and then maintain the “H” level up to the trailing edge between the points of time 8 and t9, then the “L” level up to the leading edge between the points of time t10 and t11, then the “H” level up to the trailing edge between the points of time t12 and t13, and thereafter the “L” level up to the point of time t15.
The “L” level value of the input signal DATA (b) is sampled in the D-FF 133 at the point of time t2 on the leading edge of the oscillation frequency clock VCLCLK (a). This allows a Q output signal (c) of the D-FF 133 to make the transition from the “H” level to the “L” level. The input signal DATA (b) is still at the “L” level without the transition of the level thereof at the point of time t4 on the next leading edge of the oscillation frequency VCOCLK (a), so that the Q output signal (c) of the D-FF 133 also maintains the “L” level without the transition of the level thereof.
The input signal DATA (b) is supposed to be at the “H” level at the point of time t6 on the next leading edge of the oscillation frequency VCLCLK (a), so that the Q output signal (c) of the D-FF 133 makes the transition from the “L” level to the “H” level. Then, the input signal DATA (b) is still at the “H” level at the point of time t8 on the next leading edge of the oscillation frequency clock VCOCLK (a), and the “H” level value thereof is sampled, so that the Q output signal (c) of the D-FF 133 maintains the “H” level without the transition of the level thereof.
When the point of time t10 comes, the input signal DATA (b) is supposed to be at the “L” level, so that the Q output signal (c) of the D-FF 133 also makes the transition from the “H” level to the “L” level. When the point of time t12 comes, the input signal DATA (b) is supposed to be at the “H” level, so that the Q output signal (c) of the D-FF 133 also makes the transition from the “L” level to the “H” level. When the point of time t14 on the next leading edge of the oscillation frequency clock VCOCLK (a) comes, the input signal DATA (b) is supposed to be at the “L” level. This allows the D-FF 133 to sample the “L” level value of the input signal DATA (b), so that the Q output signal (c) of the D-FF 133 makes the transition from the “H” level to the “L” level.
On the one hand, the oscillation frequency clock VCOCLK (a) with an inverted polarity is supplied to the D-FF 134 as CLK input thereof. Thus, the D-FF 134 is supposed to sample the input signal DATA at the points of time t1, t3, t5, t7, t11, t13 and t15 on the trailing edge of the oscillation frequency clock VCOCLK (a).
The Q output signal (c) of the D-FF 133 is supposed to be at the “H” level at the point of time t1, so that a Q output signal (d) of the D-FF 134 becomes “H”, and thereafter, maintains the “H” level up to the point of time t3 on the next trailing edge of the oscillation frequency clock VCOCLK (a). When the point of time t3 comes, the Q output signal (c) of the D-FF 133 is supposed to be at the “L” level, so that sampling the “L” level value thereof allows the Q output signal (d) of the D-FF 134 to make the transition from the “H” level to the “L” level. Then, the Q output signal (d) thereof maintains the “L” level up to the point of time immediately before the point of time t7 after going through the point of time t5.
The Q output signal (c) of the D-FF 133 is supposed to be at the “H” level at the point of time t7 on the next trailing edge of the oscillation frequency clock VCLCLK (a), so that sampling the “H” level value thereof allows the Q output signal (d) of the D-FF 134 to make the transition from the “L” level to the “H” level. The level of the Q output signal (c) of the D-FF 133 remains unchanged at the point of time t9. The Q output signal (c), however, makes the transition from the “H” level to the “L” level at the point of time t10 and then maintains the “L” level up to the point of time t12. The Q output signal (c) of the D-FF 133 is supposed to be at the “L” level at the point of time t11, so that sampling the “L” level value thereof in the D-FF 134 allows the Q output signal (d) of the D-FF 134 to make the transition from the “H” level to the “L” level.
The Q output signal (c) of the D-FF 133 is supposed to be at the “H” level at the point of time t13, so that sampling the “H” level value thereof in the D-FF 134 allows the Q output signal (d) of the D-FF 134 to make the transition from the “L” level to the “H” level. Information on the “H” level thereof is maintained up to the point of time t15 on the next trailing edge of the oscillation frequency clock VCLCLK (a), and the “L” level value of the Q output signal (c) of the D-FF 133 is then sampled in the D-FF 134. This allows the Q output signal (d) of the D-FF 134 to make the transition from the “H” level to the “L” level.
An operation of the EX-OR gate 135 that generates an UP pulse signal (e) will be now described with reference to the timing chart of FIG. 20. Incidentally, assume that the input signal DATA (b) and the Q output signal (c) of the D-FF 133 are respectively supplied to the two input terminals A and B of the EX-OR gate 135.
It is also assumed that the period in which the input signal DATA (b) is different in logic value from the Q output signal (c) of the D-FF 133 is one between the point of time at which the input signal DATA (b) is supposed to make the transition from the “H” level to the “L” level between the points of time t1 and t2 and the point of time t2 at which the Q output signal (c) of the D-FF 133 is supposed to be at the “H” level, one between the point of time at which the input signal DATA (b) is supposed to make the transition from the “L” level to the “H” level between the points of time t5 and t6 and the point of time t6 at which the Q output signal (c) of the D-FF 133 is supposed to make the transition from the “L” level to the “H” level, one between the point of time at which the input signal DATA (b) is supposed to make the transition from the “H” level to the “L” level between the points of time t8 and t9 and the point of time t10, one between the point of time at which the input signal DATA (b) is supposed to make the transition from the “L” level to the “H” level between the points of time t10 and t11 and the point of time t12 and one between the point of time at which the input signal DATA (b) is supposed to make the transition from the “H” level to the “L” level between the points of time t12 and t13 and the point of time t14.
Then, an output signal (e) of the EX-OR gate 135 is supposed to be at the “H” level in the above periods. On the other hand, the input signal DATA (b) and the Q output signal (c) of the D-FF 133 are respectively supposed to be at the “H” level or the “L” level in the periods other than the above periods, so that the output signal (e) of the EX-OR gate 135 becomes “L”. The output signal (e) of the EX-OR gate 135 is adapted for the UP pulse signal.
An operation of the EX-OR gate 136 that generates a DOWN pulse signal (f) will be now described with reference to the timing chart of FIG. 20. Incidentally, assume that the Q output signal (c) of the D-FF 133 and the Q output signal (d) of the D-FF 134 are respectively supplied to the two input terminals A and B of the EX-OR gate 136.
It is also assumed that the period in which the Q output signal (c) of the D-FF 133 is different in logic value from the Q output signal (d) of the D-FF 134 is one between the points of time t2 and t3, one between the points of time t6 and t7, one between the points of time t10 and t11, one between the points of time t12 and t13 and one between the points of time t14 and t15.
Then, the output signal (f) of the EX-OR gate 136 is supposed to be at the “H” level in the above periods. On the other hand, the Q output signal (c) of the D-FF 133 and the Q output signal (d) of the D-FF 134 are respectively supposed to be at the “H” level or the “L” level in the periods other than the above periods, so that the output signal (f) of the EX-OR gate 136 “L”. The output signal (f) of the EX-OR gate 136 is adapted for the DOWN pulse signal.
As described above, the pulse waveforms of the UP pulse signal (e) and the DOWN pulse signal (f) are respectively generated one at a time on every transition of the input signal DATA. The circuit configuration described above is adaptable to provide the DOWN pulse signal (f) whose pulse width is always constant, so that a phase control takes place by adjusting the pulse width of the UP pulse signal (e).
In the absence of the duty distortion in the input signal DATA, the oscillation frequency clock VCOCLK of the VCO 106 is locked to the input signal DATA under a control based on each control signal (the UP pulse signal and the DOWN pulse signal) of the frequency detection circuit 102 and the phase detection circuit 101, thereby providing the point of time on the leading edge of the clock signal ICLK so as to be positioned at the center of an eye pattern of the input signal DATA, as shown in the timing chart of FIG. 21.
On the other hand, the frequency detection circuit 102 is supposed to sample the values (the levels) of the clock signals ICLK and QCLK at the change point of the input signal DATA as described above, thereby providing the frequency information by using the sampled values thereof. In this case, if a phase relation between the clock signal ICLK and the input signal DATA is assumed to be one as shown in FIG. 21, the point of time on the trailing edge of the clock signal ICLK may be coincident with the change point of the input signal DATA.
Thus, the frequency detection circuit 102 is supposed to provide the unstable sampled value of the clock signal ICLK at the change point of the input signal DATA in proportion as the duty ratio of the input signal DATA is varied (provided that the sampled value of the clock signal QCLK is more stable than that of the clock signal ICLK). At this time, a wrong detection on the frequency information takes place in the frequency detection circuit 102, resulting in a generation of an erroneous control signal.
As described above, in the conventional PLL circuit having the phase detection circuit 101 and the frequency detection circuit 102, the clock signals ICLK and QCLK are sampled in the frequency detection circuit 102 at the change point of the input signal DATA. Thus, the presence of the duty distortion in the input signal DATA causes the frequency detection circuit 102 to output the erroneous control signal (the UP pulse signal and the DOWN pulse signal).
In addition, when the oscillation frequency clock VCLCLK of the VCO 106 is locked to the input signal DATA, the operation of the phase detection circuit 101 provides the eye pattern center of the input signal DATA so as to be positioned at the point of time on the leading edge of the clock signal ICLK. Thus, the frequency detection circuit 102 is supposed to provide the unstable sampled value of the clock signal ICLK in proportion as the duty ratio of the input signal DATA is slightly varied, resulting in the generation of the erroneous control signal from the frequency detection circuit 102.